As technology advances into the regime of sub-100 nm gate lengths in order to increase transistor speed in MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices, there is a need to improve the reliability and performance of n-type (hereafter called NMOS) and p-type (hereafter called PMOS) transistors. A typical MOSFET is shown in FIG. 1 and is comprised of a substrate 10 with insulating regions 11 that separate active areas upon which a gate oxide 12 and a gate electrode 13 are formed. A cap layer (not shown) is optional above gate electrode 13 which is also referred to as a gate conductor layer. Sidewall spacers 14 are adjacent to gate electrode 13. Source/drain regions comprised of lightly doped 15 and heavily doped 16 regions are located on either side of a channel region 17. Typically, a silicide layer 18 is formed above the gate electrode 13 and above source/drain regions 16.
When the device design shrinks to provide faster transistors, the gate length (width of gate electrode 13) and channel length become shorter. One effect of a shorter channel is a hot carrier effect (HCE) that occurs when electrons introduced to a strong electric field near the drain region 16 generate hot carriers that can accumulate in the gate oxide 12. A build up of hot carriers can cause changes in the threshold voltage (Vt) and reduce the reliability of the MOSFET. Therefore, a need exists to reduce the hot carrier lifetime and improve Vt stability.
Silicon nitride is often used as an etch stop layer in device fabrication. For example, a layer of silicon nitride is deposited on a substrate and a dielectric layer is formed over the nitride layer. Then contact holes are etched into the dielectric layer and stop on the nitride because of a high etch selectivity toward an oxide based dielectric layer. Etch selectivity of silicon nitride relative to oxide is higher than silicon oxynitride relative to oxide. When the substrate in the aforementioned structure is a MOS transistor and interconnects are subsequently formed to the source/drain regions and to the gate electrode through the dielectric layer and nitride, care must exercised in depositing the nitride. Otherwise, hot carrier lifetime and Vt stability are significantly degraded compared to results obtained with silicon oxynitride as the etch stop. Silicon nitride tends to have a high hydrogen content that passivates dangling bonds between the Si/SiO2 interface. However, the Si—H bonds formed at the interface can easily be broken during HCE and Vt stress which leads to a longer HCE lifetime and poorer Vt stability. Therefore, an improved method of forming a silicon nitride etch stop layer is required to improve reliability and N/PMOS performance, especially saturated drain current (Idsat).
U.S. Pat. No. 6,372,672 describes a PECVD method of depositing a silicon nitride layer that exhibits good stress characteristics during thermal processing. A combination of SiH4, NH3, and N2 is employed with a SiH4/NH3 ratio of from 2:1 to 1:3. The flow rates, RF power, and chamber pressure are controlled to give a composition of Si3N3.75H0.25 which is lower in hydrogen content than the conventional nitride film that is about Si3N3.33H0.67. The process deposits a nitride layer at a rate of 1500 Angstroms per minute.
In contrast to the high rate of deposition cited in the previous case, U.S. Pat. No. 5,731,238 describes a jet vapor deposition (JVD) of silicon nitride without a hydrogen containing nitride source gas at a rate of between 3 and 10 Angstroms per minute. The resulting JVD nitride has a hydrogen content of less than 10 atomic % compared to 20 to 30 atomic % in conventional silicon nitride layers. Stress induced leakage current in non-volatile memory cells is reduced.
U.S. Pat. No. 6,284,583 mentions formation of a silicon nitride film by a low pressure CVD process involving SiCl4 and ammonia. The hydrogen density per unit area is less than 1×1015 cm−2 and the layer is substantially free of Si—H bonds. The nitride layer serves as a capacitor insulating film and leakage current is suppressed when hydrogen density is minimized.
Related art in U.S. Pat. No. 4,563,367 describes an apparatus and method for forming silicon nitride films in a plasma assisted CVD process. The process involves SiH4, NH3, and N2 and provides a deposition rate of 300 to 400 Angstroms per minute.
In one example found in U.S. Pat. No. 6,372,569, a hydrogen rich silicon nitride layer is formed over a NMOS transistor. A dielectric layer which is subsequently deposited on the nitride is densified at 600° C. to 800° C. to drive the hydrogen in the nitride layer into an underlying source/drain region to improve the saturated drain current (Idsat).
Another modification of a silicon nitride layer is found in U.S. Pat. No. 5,897,372 where a silicon rich nitride is used as a protective layer in self aligned etching. The conformal silicon rich nitride has a higher resistance to a fluorocarbon etch than conventional nitride because less nitrogen is present in the film to react with and remove a protective carbon build up that is formed during the etch.